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| Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM Document Title 2M x 16 bit Pseudo SRAM ( EMP216MEAF Series ) Specification Revision History Revision No. 0.0 History Initial Draft Draft Date Oct. 24 , 2005 Remark Preliminary 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Emerging Memory & Logic Solutions Inc. Zip Code : 690-717 The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM 2Mb x16 Pseudo Static RAM Specification GENERAL DESCRIPTION The EMP216MEAF series is 33,554,432 bits of Pseudo SRAM which uses DRAM type memory cells, but this device has refresh-free operation and extreme low power consumption technology. Furthermore the interface is compatible to a low power Asynchronous type SRAM. The EMP216MEAF is organized as 2,097,152 Words x 16 bit. FEATURES - Organization :2M x16 - Power Supply Voltage : 2.7 ~ 3.3V - Separated I/O power(VccQ) & Core power(Vcc) - Three state outputs - Byte read/write control by UB# / LB# - Support Page Read/Write operation with 16 words - Support PASR, RMS, DPD and Auto-TCSR for power saving - Package type : 48-FPBGA 6.0x8.0 PRODUCT FAMILY Part Number Operating Temp. Power Supply Speed (tRC) Power Dissipation (ISB1, Max.) Standby (ICC2, Max.) Operating EMP216MEAF-70E -25oC to 85oC 2.7V to 3.3V 70ns 100uA 25mA FUNCTION BLOCK DIAGRAM ZZ# CS# UB# LB# WE# OE# Self-Refresh CONTROL CONTROL LOGIC COLUMN SELECT ROW SELECT A0~A20 ADDRESS DECODER Memory Array 2M X 16 DQ0~ DQ15 Din/Dout BUFFER I/O CIRCUIT Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM PIN DESCRIPTION ( 48-FBGA-6.00x8.00 ) 1 A LB# 2 OE# 3 A0 4 A1 5 A2 6 ZZ# B DQ8 UB# A3 A4 CS# DQ0 C D DQ9 DQ10 A5 A6 DQ1 DQ2 VSSQ DQ11 A17 A7 DQ3 VCC E VCCQ DQ12 DNU A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G H DQ15 A19 A12 A13 WE# DQ7 A18 A8 A9 A10 A11 A20 TOP VIEW (Ball Down) Name CS# OE# WE# ZZ# Function Chip select inputs Output enable input Write enable input Low Power Control Name LB# UB# VCC VCCQ Function Lower byte (DQ0~7) Upper byte (DQ8~15) Power supply I/O Power supply DQ0-15 Data In-out A0-20 DNU Address inputs Do Not Use VSS(Q) Ground NC No connection Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM ABSOLUTE MAXIMUM RATINGS 1) Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage Temperature Operating Temperature Symbol VIN, VOUT VCC, VCCQ PD TSTG TA Ratings -0.2 to VCCQ+0.3V -0.22) to 3.6V 1.0 -65 to 150 -25 to 85 Unit V V W o o C C 1. Stresses greater than those listed above "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Undershoot at power-off : -1.0V in case of pulse width < 20ns FUNCTIONAL DESCRIPTION CS# H H X L L L L L L L L ZZ# H L H H H H H H H H H OE# X X X H H L L L X X X WE# X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L DQ0~7 High-Z High-Z High-Z High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In DQ8~15 High-Z High-Z High-Z High-Z High-Z High-Z Data Out Data Out High-Z Data In Data In Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Stand by Low Power Mode Stand by Active Active Active Active Active Active Active Active Note: X means don't care. (Must be low or high state) Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Supply voltage Ground Input high voltage Input low voltage 1. 2. 3. 4. Symbol VCC VCCQ VSS, VSSQ VIH VIL Min 2.7 2.7 0 0.8 * VCCQ -0.23) Typ 3.0 3.0 0 - Max 3.3 3.3 0 VCCQ + 0.22) 0.2 * VCCQ Unit V V V V V TA= -25 to 85oC, otherwise specified Overshoot: VCC +1.0 V in case of pulse width < 20ns Undershoot: -1.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f =1MHz, TA=25oC) Item Input capacitance Input/Ouput capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 8 Unit pF pF DC AND OPERATING CHARACTERISTICS Parameter Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage VOL VOH ISB Test Conditions VIN=VSS to VCCQ , VCC=VCCmax CS#=VIH , ZZ#=VIH , OE#=VIH or WE#=VIL , VIO=VSS to VCCQ , VCC=VCCmax Cycle time=1s, 100% duty, IIO=0mA, CS#<0.2V, ZZ#=VIH , VIN<0.2V or VIN>VCCQ-0.2V Cycle time = Min, IIO=0mA, 100% duty, CS#=VIL, ZZ#=VIH, VIN=VIL or VIH IOL = 0.5mA, VCC=VCCmin IOH = -0.5mA, VCC=VCCmin CS#,ZZ#>VCCQ-0.2V, Other inputs = 0 ~ VCCQ (Typ. condition : VCC=3.0V @ 25oC) (Max. condition : VCC=3.3V @ 85oC) Min -1 -1 0.8*VCCQ Typ - Max 1 1 3 25 0.2*VCCQ Unit uA uA mA mA V V - Standby Current (CMOS) - - 100 uA 1. Maximum Icc specifications are tested with VCC = VCCmax. Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.2V to VCCQ-0.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : VCCQ/2 Output Load (See right) : CL = 30pF 1. Including scope and Jig capacitance 1) Dout CL1) AC CHARACTERISTICS (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = -25C to +85oC) Parameter List Read Cycle Time Address access time Chip enable to data output Output enable to valid output UB#, LB# enable to data output Read Chip enable to low-Z output UB#, LB# enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB#, LB# disable to high-Z output Output disable to high-Z output Output hold from Address change Write Cycle Time Chip enable to end of write Address setup time Address valid to end of write UB#, LB# valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z Maximum cycle time Page Page mode cycle time Page mode address access time Symbol tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW tMRC tPC tPAA Speed Min 70 10 10 5 0 0 0 5 70 60 0 60 60 50 0 0 20 0 5 25 Max 20k 70 70 25 70 15 15 15 20k 15 20k 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM TIMING DIAGRAMS READ CYCLE (1) (Address controlled, CS#=OE#=VIL, ZZ#=WE#=VIH, UB# or/and LB#=VIL) tRC Address tOH Data Out Previous Data Valid tAA Data Valid READ CYCLE (2) (ZZ#=WE#=VIH) tRC Address tAA CS# LB#, UB# OE# Data Out High-Z tCO tBA tOE tOH tHZ tBHZ tOHZ Data Vaild tOLZ tLZ tBLZ NOTES (READ CYCLE) 1. tHZ , tBHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. Do not Access device with cycle timing shorter than tRC for continuous periods > 20us. |||| Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM PAGE READ CYCLE (ZZ#=WE#=VIH, 16 Words access) tMRC Address (A20~A4) tRC Address (A3~A0) tPC tPC tPC tPC tAA tCO tOH CS# tBA LB#,UB# tOE OE# Data Out tOLZ High-Z tHZ tBHZ tPAA Data Valid tPAA Data Valid tPAA Data Valid tPAA Data Valid tOHZ Data Valid tBLZ tLZ NOTES (READ CYCLE) 1. tHZ , tBHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. Do not Access device with cycle timing shorter than tRC for continuous periods > 20us. Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM WRITE CYCLE (1) (WE# controlled, ZZ#=VIH) Address CS# LB#,UB# WE# tAS Data In Data Out High-Z tWHZ Data Undefined tWC tAW tCW tBW tWP tDW Data Valid tWR tDH tOW WRITE CYCLE (2) (CS# controlled, ZZ#=VIH) Address tAS tWC tCW tAW tWR CS# LB#,UB# WE# tBW tWP tDW tDH Data In Data Out High-Z Data Valid WRITE CYCLE (3) (UB#/LB# controlled, ZZ#=VIH) tWC Address tCW CS# tAW LB#,UB# WE# tAS tBW tWP tDW Data In Data Out High-Z tWR tDH Data Valid Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM PAGE WRITE CYCLE (ZZ#=VIH, 16 Words access) tMRC Address (A20~A4) tWC Address (A3~A0) tPC tPC tPC tPC CS# LB#,UB# tAS WE# tDW Data In High-Z tDH tDW tDH tDW tDH tDW tDH tDW tDH tWHZ Data Valid Data Valid Data Valid Data Valid Data Valid tOW Data Out NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS#, low WE# and low UB# or LB#. A write begins at the last transition among low CS# and low WE# with asserting UB# or LB# low for single byte operation or simultaneously asserting UB# and LB# low for word operation. A write ends at the earliest transition among high CS# and high WE#. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from CS# going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS# or WE# going high. 5. Do not Access device with cycle timing shorter than tWC for continuous periods > 20us. (c)(c)(c)(c) Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM LOW POWER MODES Mode Register Set A20 ~ A5 All 0 (Reserved for future) A4 DPD Enable/Disable A3 Array Mode Selection A2 Array Half Selection A1 A0 Array Refresh Area Selection DPD Enable / Disable A4 0 1 Type Deep Power Down Enable DPD Disable (Default) Array Mode Selection A3 0 1 Type Partial Array Refresh Mode (Default) Reduced Memory Size Mode Array Half Selection (Top/Down) A2 0 1 Type Bottom (Default) Top Array Refresh Area Selection A1 0 0 1 1 A0 0 1 0 1 Type Full Array (Default) RFU (Reserved for future) 1/2 Array 1/4 Array NOTES 1. The Partial Array Refresh and Deep Power Down mode is issued only during ZZ# low state. 2. The RMS (Reduced Memory Size) mode is enabled after ZZ# goes high and remains enabled after ZZ# goes high. To change to a different mode, the mode register will have to be re-written. 3. If register is written to enable the Deep Power Down, the part will go into Deep Power Down during the following time that ZZ# is driven low and there is no MRS update. When ZZ# is driven high, all of the register settings will return to dafault state for the part (i.e. full array refresh, Deep Power Down disabled.) Mode Register Set UpdateTiming Diagram tWC Address tCW CS# LB#,UB# WE# tZZWE ZZ# NOTES Register write start tWR tAS tAW tBW tWP Register write complete Register update complete The register update takes place after over the tZZWE maximum time of 1us. Once the register is updated the next time ZZ# goes low, without any updates to the register starting within the tZZWE maximum time of 1us, the part will refresh the array selected. The data bus is a don't care when ZZ# is low during the register updates. Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM LOW POWER MODES Deep Power Down Mode Entry & Exit A4 tCW CS# tAS tAW UB#,LB# tWP WE# tZZWE ZZ# Register Write Start tWR tZZmin ~ ~ ~~ ~~ ~~ ~~ tBW ~ ~ ~~ ~~ tWC tR Deep Power Down Exit Normal operation Parameter tZZWE tR(Deep Power Down mode only) tZZmin Description ZZ# low to Write Enable Low Operation Recovery Time Low Power Mode Time Min 0 200 10 Max 1 - Unit us us us Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM Address Information for PASR mode and RMS mode Partial Array Self Refresh Mode (A3=0, A4=1) A2 0 0 X 1 1 A1 1 1 0 1 1 A0 1 0 0 1 0 Refresh Section 1/4 1/2 Full 1/4 1/2 Address 000000h~07FFFFh 000000h~0FFFFFh 000000h~1FFFFFh 180000h~1FFFFFh 100000h~1FFFFFh Size 512Kb x 16 1Mb x 16 2Mb x 16 512Kb x 16 1Mb x 16 Density 8Mb 16Mb 32Mb 8Mb 16Mb Reduced Memory Size Mode (A3=1, A4=1) A2 0 0 1 1 A1 1 1 1 1 A0 1 0 1 0 Refresh Section 1/4 1/2 1/4 1/2 Address 000000h~07FFFFh 000000h~0FFFFFh 180000h~1FFFFFh 100000h~1FFFFFh Size 512Kb x 16 1Mb x 16 512Kb x 16 1Mb x 16 Density 8Mb 16Mb 8Mb 16Mb Low Power Mode Characteristics Parameter Deep Power Down Current Partial Array Refresh Mode Standby Current Reduced Memory Size Mode Standby Current Symbol IZZ IZZa IZZb ISB1a ISB1b ZZ# < 0.2V, Other inputs = 0 ~ VCCQ (Max. condition : VCC=3.3V @ 85oC) Test Conditions Array No Refresh 1/4 Array 1/2 Array Min - Typ - Max 10 65 75 65 75 Unit uA uA uA uA uA RMS mode. Other inputs = 0 ~ VCCQ (Max. condition : VCC=3.3V @ 85oC) 1/4 Array 1/2 Array Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM TIMING WAVEFORM OF POWER UP 200us VCC(Min.) VCC CS# Power Up Mode Normal Operation NOTE ( POWER UP ) 1. After Vcc reaches Vcc(Min.) , wait 200us with CS# high. Then you get into the normal operation. Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM PACKAGE DIMENSION 48 Ball Fine Pitch BGA (0.75mm ball pitch) Top View A1 corner index area Bottom View B B1 6 A B C C1 C B/2 5 4 3 2 1 A1 index Mark B C D E C/2 F G H Side View 4 E2(Seating plane) A 3 D(Diameter) 0.25 Typ. C Detail A A 5 E1 E R C Min. A B B1 C C1 D E E1 E2 R 5.90 7.90 0.30 0.20 Typ. 0.75 6.00 3.75 8.00 5.25 0.35 1.00 0.75 0.25 Max. 6.10 8.10 0.40 1.10 0.30 0.08 0.75 Typ. NOTES 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. All dimensions are millimeters. 3. Dimension "D" is measured at the maximum solder ball diameter in a plane parallel to datum C. 4. Primary datum C (Seating plane) is defined by the crown of the solder balls. 5. This is a controlling dimension. Rev 0.0 |
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